1. Field of the Invention
The present invention relates to buffer circuits, and particularly to a buffer circuit which transfers small amplitude signals in synchronization with a clock signal. More particularly, the present invention relates to a read data transferring buffer circuit for transferring internal read data in synchronization with a clock signal in a semiconductor memory device.
2. Description of the Background Art
In order to improve data transfer efficiency, the bit width of data to be dealt in a semiconductor device has been frequently made larger in recent years. Such internal data with a lager bit width are transferred in parallel on an internal data bus with a larger bit width. In a semiconductor device which operates in synchronization with a clock signal, internal data are transferred by using buffer circuits operating in synchronization with the clock signal. Since the buffer circuits provided for bus lines of the internal data bus operate in parallel, the larger bit width of the internal data results in increase in number of the buffer circuits operating in parallel, and increase in power consumption when the internal data are transferred.
The power consumption is reduced by forming the internal data bus into a pair of complementary data lines and transmitting one-bit data in the form of a pair of complementary signals. Because of pair of the complementary signals of data on the internal data line pair can be dealt as small amplitude signals which in turn have their amplitudes smaller than a power supply potential. Thus, the need to fully swing the internal data bus lines between power supply and ground voltages is eliminated, and the power consumption is reduced. When such data in the form of small amplitude signals is to be transferred, the buffer circuit amplifies the small amplitude signals.
FIG. 1 shows one example of the arrangement of a buffer circuit transferring a small amplitude signal. In FIG. 1, the transfer buffer includes a transfer gate la to transmit complementary internal read data signals DIN, /DIN to amplifier nodes AN, /AN in response to a transfer control signal TXA, an amplifier circuit 2 to amplify the signals on the amplifier nodes in response to amplifier activation signal AME, and a transfer gate 1b to transfer the signals on amplifier nodes AN, /AN in response to a transfer control signal TXB.
Internal data signals DIN, /DIN are small amplitude signals, and amplifier circuit 2 amplifies the small amplitude signals to signals having a power supply voltage level amplitude by the amplification operation. Therefore, transfer data signals DO, /DO from transfer gate 1b become CMOS level signals if transfer gate 1b is conductive for a sufficient period. In the following, the operation of the transfer buffer circuit shown in FIG. 1 will be described with reference to a timing chart shown in FIG. 2.
In data transfer, transfer control signals TXA, TXB are activated for a prescribed period in response to a clock signal CLK. First, transfer control signal TXA attains the high level for a prescribed period in synchronization with a rise of clock signal CLK, transfer gate la is rendered conductive, and internal data signals DIN, /DIN are transmitted to amplifier nodes AN, /AN. When the signal potentials on amplifier nodes AN, /AN change sufficiently, amplifier activation signal AME is activated, and the small amplitude signals on amplifier nodes AN, /AN are amplified to signals having power supply and ground voltage levels. When the potentials on amplifier nodes AN, /AN are stabilized, transfer control signal TXB is then activated in response to a fall of clock signal CLK, transfer gate 1b is rendered conductive, and the potentials of transfer data signals DO, /DO change according to the signal potentials on amplifier nodes AN, /AN. When the potentials of transfer data signals DO, /DO change sufficiently, transfer control signal TXB is inactivated and, thereafter or simultaneously, amplifier circuit 2 is also inactivated.
By changing transfer control signals TXA, TXB in synchronization with clock signal CLK so as to transfer signals, data can be output in synchronization with the clock signal in a clock synchronous type semiconductor memory device, for example.
As indicated by the dashed lines in FIG. 1, amplifier nodes AN, /AN have parasitic capacitance due to the gate capacitance and interconnection lines of amplifier circuit 2. The parasitic capacitance accumulates electric charges corresponding to data signals amplified by amplifier circuit 2 in a previous cycle. Therefore, if transfer control signal TXA attains the high level and transfer gate la is rendered conductive, electric charges accumulated in the parasitic capacitance flow out to the internal data lines as shown in FIG. 3A. If a circuit drivability for the internal data lines is small, the voltage levels of small amplitude signals or internal data signals DIN, and /DIN may change. Especially if data corresponding to the electric charges accumulated on amplifier nodes AN, /AN is an inversion of the data represented by internal data signals DIN, /DIN, the potential levels of small amplitude data signals DIN, /DIN change. If the amplitudes of internal data signals DIN, /DIN are small, therefore, the amplification operation cannot be performed correctly. Even if the potential levels of small amplitude data signals DIN, /DIN are not inverted, the potential difference between small amplitude signals DIN, /DIN becomes much smaller due to the outflow of electric charges from amplifier nodes AN, /AN, signals with a sufficient amplitude cannot be transmitted to amplifier nodes AN, /AN, and the data amplification operation cannot be performed correctly by amplifier circuit 2 as a result.
Since data is transferred at high speed, if the period during which transfer control signal TXA is active (at the high level) is short as shown in FIG. 3B, sufficient electric charges cannot be transmitted to amplifier nodes AN, IAN even when electric charges do not flow out. Therefore, the signal amplitudes (potential difference) on amplifier nodes AN, /AN are small, and thus amplifier circuit 2 cannot perform the amplification operation correctly.
Therefore, when the power consumption is reduced by transferring internal data in the form of small amplitude complementary signals, the signal amplitudes can be reduced. However, if the speed of clock signal CLK is made higher, then the data cannot be transferred correctly and in synchronization with the clock signal.
The problem as described above is generally observed, for example, in a buffer circuit such as an interface circuit for processing small amplitude signals, not limited to a semiconductor memory device.
An object of the present invention is to provide a transfer buffer circuit capable of transmitting a signal at high speed in synchronization with a clock signal.
Another object of the present invention is to provide a transfer buffer circuit occupying a small area, consuming a smaller amount of power, and capable of correctly transferring a small amplitude signal at high speed.
A transfer buffer circuit according to the present invention includes an equalize circuit coupled to a pair of internal nodes for equalizing the pair of internal nodes to a prescribed potential, a transfer gate circuit coupled between a pair of first signal lines and the pair of internal nodes for coupling the pair of first signal lines and the pair of internal nodes after equalization is completed, an amplifier circuit for differentially amplifying signals on the pair of internal nodes after transfer is completed by the transfer gate circuit complete the transfer operation, an output transfer circuit for driving a pair of second signal lines according to the signals on the pair of internal nodes in response to an output control signal after the amplifier circuit completes the amplification flow operation, and a control circuit for controlling the operations of the equalize circuit, the transfer gate circuit, the amplifier circuit and the output transfer circuit according to at least a clock signal.
Since the internal nodes of the transfer gate circuit are equalized to a prescribed potential and then supplied with signals to be transferred, the signals, even if they are small amplitude signals, can be transferred without amplitude destruction. Since the control circuit is provided in the transfer buffer circuit, even if a plurality of transfer buffer circuits are provided in parallel, equalization, amplification and transfer can be individually and reliably performed in synchronization with at least the clock signal in each transfer buffer circuit. Therefore, without taking into account signal skew, the signals can be transferred correctly in synchronization with a clock signal even if it is a high speed clock signal is.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.